There is a continuous strive to make integrated circuits smaller and denser. Integrated circuits typically comprise multi-level interconnect structures. Such a structure may include a number of vertically stacked interconnection levels, each comprising horizontally extending conductive paths or lines arranged in a dielectric layer. Conductive paths of adjacent interconnection levels may be interconnected by vertically extending connections known as vias extending vertically between conductive paths of two interconnection levels.
In conventional circuit fabrication, an interconnection level is typically formed in what in the art is known as a “dual damascene process”. According to this approach horizontally extending trenches are etched in a dielectric layer. Further, vertically extending via holes are formed in the dielectric layer. Thereafter the trenches and via holes are simultaneously filled with a conductive material to form conductive lines in the trenches and conductive vias in the via holes. The process may be repeated to form a stack of interconnection levels.
To enable more area efficient and flexible signal routing within an interconnect structure it has been proposed to incorporate so-called multi-level vias or “supervias”. A multi-level via is a via which directly interconnects two non-adjacent interconnection levels and electrically bypasses an intermediate level. Although multi-level vias is a promising concept, designing viable integration processes for forming interconnection structures comprising such multi-level vias however remains a challenge.